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1/16 not for new design november 2000 this is information on a product still in production but not recommended for new designs. mk41t56 MKI41T56 512 bit (64b x8) serial access timekeeper ? sram n counters for seconds, minutes, hours, day, date, month and years n software clock calibration n automatic power-fail detect and switch circuitry n i 2 c bus compatible n 56 bytes of general purpose ram n ultra-low battery supply current of 500na n operating temperature: C mk41t56: 0 to 70c C MKI41T56: C40 to 85c n automatic leap year compensation description the mk41t56 timekeeper ? is a low power 512 bit static cmos ram organized as 64 words by 8 bits. a built-in 32.768khz oscillator (external crys- tal controlled) and the first 8 bytes of the ram are used for the clock/calendar function and are con- figured in binary coded decimal (bcd) format. ad- dresses and data are transferred serially via a two- line bi-directional bus. the built-in address register is incremented automatically after each write or read data byte. the mk41t56 clock has a built-in power sense circuit which detects power failures and automatically switches to the battery supply during power failures. the energy needed to sus- tain the ram and clock operations can be supplied from a small lithium button cell. data retention time is in excess of 10 years with a 50mah 3v lithium cell. the mk41t56 is supplied in 8 pin plastic dual-in-line and 8 lead plastic soic packages. figure 1. logic diagram ai02304 osci v cc mk41t56 MKI41T56 v ss scl osco sda ft/out v bat 8 1 8 1 so8 (m) 150mil width psdip8 (n) 0.4mm frame
mk41t56, MKI41T56 2/16 figure 2. dip connections sda v ss scl ft/out osco osci v cc v bat ai02305 mk41t56 MKI41T56 1 2 3 4 8 7 6 5 device can then be accessed sequentially in the following order: 1. seconds register 2. minutes register 3. hours register 4. day register 5. date register 6. month register 7. years register 8. control register 9 to 64. ram the clock continually monitors v cc for an out of tolerance condition. should v cc fall below v pfd , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to pre- vent erroneous data from being written to the de- vice from an out of tolerance system. when v cc falls below v bat , the device automatically switch- es over to the battery and powers down into an ul- tra low current mode of operation to conserve battery life. upon power-up, the device switches from battery to v cc at v bat and recognizes inputs when v cc goes above v pfd volts. figure 3. soic connections 1 sda v ss scl ft/out osco osci v cc v bat ai02306 mk41t56 MKI41T56 2 3 4 8 7 6 5 table 1. signal names osci oscillator input ocso oscillator output ft/out frequency test / output driver (open drain) sda serial data address input / output scl serial clock v bat battery supply voltage v cc supply voltage v ss ground operation the mk41t56 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave ad- dress (11010000). the 64 bytes contained in the
3/16 mk41t56, MKI41T56 table 2. absolute maximum ratings note: stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a st ress rating only and functional operation of the device at these or any other conditions above those indicated in the operational se ction of this specification is not implied. exposure to the absolute maximum rating conditions for extended periods of time may affect r eliability. caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. table 3. register map symbol parameter value unit t a ambient operating temperature mk41t56 0 to 70 c MKI41T56 C40 to 85 c t stg storage temperature (v cc off, oscillator off) C55 to 125 c v io input or output voltages C0.3 to 7 v v cc supply voltage C0.3 to 7 v i o output current 20 ma p d power dissipation 0.25 w address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 0 st 10 seconds seconds seconds 00-59 1 x 10 minutes minutes minutes 00-59 2 x x 10 hours hours hour 00-23 3 xxxxx day day 01-07 4 x x 10 date date date 01-31 5 x x x 10 m. month month 01-12 6 10 years years year 00-99 7 out ft s calibration control keys: s = sign bit ft = frequency test bit st = stop bit out = output level x = dont care
mk41t56, MKI41T56 4/16 table 4. ac measurement conditions note that output hi-z is defined as the point where data is no longer driven. input rise and fall times 5ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v figure 5. ac testing load circuit ai01019 5v out c l = 100pf c l includes jig capacitance 1.8k w device under test 1k w figure 4. block diagram ai00586c seconds oscillator 32.768 khz voltage sense and switch circuitry serial bus interface divider control logic address register minutes hours day date month year control ram (56 x 8) osci osco ft/out v cc v ss v bat scl sda 1 hz
5/16 mk41t56, MKI41T56 table 5. capacitance (1, 2) (t a = 25 c, f = 1 mhz) note: 1. effective capacitance measured with power supply at 5v. 2. sampled only, not 100% tested. 3. outputs deselected. table 6. dc characteristics (t a = 0 to 70c or C40 to 85c; v cc = 4.5v to 5.5v) note: 1. the rayovac br1225 or equivalent is recommended as the battery supply. table 7. power down/up trip points dc characteristics (1) (t a = 0 to 70c or C40 to 85c) note: 1. all voltages referenced to v ss . table 8. crystal electrical characteristics (externally supplied) note: load capacitors are integrated within the mk41t56. circuit board layout considerations for the 32.768khz crystal of minimu m trace lengths and isolation from rf generating signals should be taken into account. stmicroelectronics recommends the ecs-.327-12.5-8sp-2 quartz crystal is recommended for industrial temperature operations. esc inc. can be contacted at 800-237-1041 or 913-782-7787 for further information on this crystal type. symbol parameter min max unit c in input capacitance (scl) 7 pf c out (2) output capacitance (sda, ft/out) 10 pf symbol parameter test condition min typ max unit i li input leakage current 0v v in v cc 10 a i lo output leakage current 0v v out v cc 10 a i cc1 supply current scl/sda = v cc C 0.3v 1ma i cc2 supply current (stand-by) 1 ma v il input low voltage C0.3 1.5 v v ih input high voltage 3v cc + 0.8 v v ol output low voltage i ol = 5ma, v cc = 4.5v 0.4 v v bat (1) battery supply voltage 2.6 3 3.5 v i bat battery supply current t a = 25c, v cc = 0v, oscillator on, v bat = 3v 450 500 na symbol parameter min typ max unit v pfd power-fail deselect voltage 1.2 v bat 1.25 v bat 1.285 v bat v v so battery back-up switchover voltage v bat v symbol parameter min typ max unit f o resonant frequency 32.768 khz r s series resistance 35 k w c l load capacitance 12.5 pf
mk41t56, MKI41T56 6/16 table 9. power down/up mode ac characteristics (t a = 0 to 70 c or C40 to 85c) symbol parameter min max unit t pd scl and sda at v ih before power down 0ns t fb v pfd (min) to v so v cc fall time 300 s t rb v so to v pfd (min) v cc rise time 100 s t rec scl and sda at v ih after power up 200 s figure 6. power down/up mode ac waveforms ai00595 v cc tfb trec tpd trb v pfd v so data retention time sda scl i bat 2-wire bus characteristics this bus is intended for communication between different ics. it consists of two lines: one bi-direc- tional for data signals (sda) and one for clock sig- nals (scl). both the sda and the scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: C data transfer may be initiated only when the bus is not busy. C during data transfer, the data line must remain stable whenever the clock line is high. C changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy. both data and clock lines remain high. start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition. stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number
7/16 mk41t56, MKI41T56 table 10. ac characteristics (t a = 0 to 70 c or C40 to 85c; v cc = 4.5v to 5.5v) note: 1. transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of scl. symbol parameter min max unit f scl scl clock frequency 0 100 khz t low clock low period 4.7 s t high clock high period 4 s t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 4s t su:sta start condition setup time (only relevant for a repeated start condition) 4.7 s t su:dat (1) data setup time 250 ns t hd:dat data hold time 0 s t su:sto stop condition setup time 4.7 s t buf time the bus must be free before a new transmission can start 4.7 s t i noise suppression time constant at scl and sda input 0.25 1 s of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. by definition, a device that gives out a message is called "transmitter", the receiving device that gets the message is called "receiver". the device that controls the message is called "master". the de- vices that are controlled by the master are called "slaves". acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge relat- ed clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low dur- ing the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must sig- nal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave the data line high to enable the master to generate the stop condition.
mk41t56, MKI41T56 8/16 figure 7. serial bus data transfer sequence figure 8. acknowledgment sequence figure 9. bus timing requirements sequence note: p = stop and s = start ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00588 data output by receiver data output by transmitter sclk from master start clock pulse for acknowledgement 12 89 data 1 data 2 data 8 ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
9/16 mk41t56, MKI41T56 write mode in this mode the master transmitter transmits to the mk41t56 slave receiver. bus protocol is shown in figure 10. following the start condi- tion and slave address, a logic '0' (r/w = 0) is placed on the bus and indicates to the addressed device that word address an will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the mk41t56 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see figure 9). read mode in this mode, the master reads the mk41t56 slave after setting the slave address (see figure 11). following the write mode control bit (r/w = 0) and the acknowledge bit, the word address an is writ- ten to the on-chip address pointer. next the start condition and slave address are repeated, followed by the read mode control bit (r/w = 1). at this point, the master transmitter becomes the master receiver. the data byte which was ad- dressed will be transmitted and the master receiv- er will send an acknowledge bit to the slave transmitter. the address pointer is only increment- ed on reception of an acknowledge bit. the mk41t56 slave transmitter will now place the data byte at address an + 1 on the bus. the master re- ceiver reads and acknowledges the new byte and the address pointer is incremented to an + 2. this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to the slave transmitter. an alternate read mode may also be implement- ed, whereby the master reads the mk41t56 slave without first writing to the (volatile) address point- er. the first address that is read is the last one stored in the pointer, see figure 12. clock calibration the mk41t56 is driven by a quartz controlled os- cillator with a nominal frequency of 32,768hz. a typical mk41t56 is accurate within 1minute per month at 25c without calibration. the devices are tested not to exceed 35ppm (parts per million) os- cillator frequency error at 25c, which equates to about 1.53 minutes per month. the oscillation rate of any crystal changes with temperature (see figure 14). most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. the mk41t56 design, however, em- ploys periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in figure 13. the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five bit calibration byte found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits in the control register. this byte can be set to represent any value between 0 and 31 in binary form. the sixth bit is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. cali- bration occurs within a 64minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 min- utes cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or C2.034ppm of adjustment per calibration step in the calibration register. assuming that the oscillator is in fact running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent 10.7 seconds per month. figure 10. slave address location ai00590 r/w slave address start a 01000 11
mk41t56, MKI41T56 10/16 figure 11. write mode sequence figure 12. read mode sequence figure 13. alternate read mode sequence ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (n) slave address ai00592b bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (n) slave address s start r/w slave address ack ai00593 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address
11/16 mk41t56, MKI41T56 dicates the degree and direction of oscillator fre- quency shift at the test temperature. for example, a reading of 512.01024hz would in- dicate a +20ppm oscillator frequency error, requir- ing a C10(xx001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency. output driver pin when the ft bit is not set, the ft/out pin be- comes an output driver that reflects the contents of d7 of the control register. in other words, when d6 of location 7 is a zero and d7 of location 7 is a zero and then the ft/out pin will be driven low. note: the ft/out pin is open drain which re- quires an external pull-up resistor. two methods are available for ascertaining how much calibration a given mk41t56 may require. the first involves simply setting the clock, letting it run for a month and comparing it to a known accu- rate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his en- vironment may require, even after the final product is packaged in a non-user serviceable enclosure. all the designer has to do is provide a simple utility that accessed the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of some test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the control register, is set to a '1', and the oscillator is running at 32,768hz, the ft/out pin of the device will toggle at 512hz. any deviation from 512hz in- figure 14. clock calibration ai00594b normal positive calibration negative calibration
mk41t56, MKI41T56 12/16 figure 15. crystal accuracy across temperature ai02124 -80 -60 -100 -40 -20 0 20 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 d f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ppm c
13/16 mk41t56, MKI41T56 table 11. ordering information scheme for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: MKI41T56 n 00 tr operating temperature blank = 0 to 70c i = C40 to 85c package n = psdip8 0.40mm frame s = so8 0.15mm frame speed 00 = no speed options shipping method for soic blank = tubes tr = tape & reel table 12. revision history date revision details march 1999 first issue 11/30/00 from data sheet to not for new design
mk41t56, MKI41T56 14/16 table 13. psdip8 - 8 pin plastic small skinny dip, 0.4mm lead frame, package mechanical data symb mm inches typ min max typ min max a C 4.80 C 0.1890 a1 0.70 C 0.0276 C a2 3.10 3.60 0.1220 0.1417 b 0.38 0.58 0.0150 0.0228 b1 1.15 1.65 0.0453 0.0650 c 0.38 0.52 0.0150 0.0205 d 9.20 9.90 0.3622 0.3898 e 7.62 C C 0.3000 C C e1 6.30 7.10 0.2480 0.2795 e1 2.54 C C 0.1000 C C ea 8.40 C 0.3307 C eb C 9.20 C 0.3622 l 3.00 3.80 0.1181 0.1496 n8 8 figure 16. psdip8 - 8 pin plastic skinny dip, 0.4mm lead frame, package outline drawing is not to scale. psdip-a a2 a1 a l e1 d e1 e n 1 c ea eb b1 b
15/16 mk41t56, MKI41T56 table 14. so8 - 8 lead plastic small outline, 150 mils body width, package mechanical data symb mm inches typ min max typ min max a 1.35 1.75 0.0531 0.0689 a1 0.10 0.25 0.0039 0.0098 b 0.33 0.51 0.0130 0.0201 c 0.19 0.25 0.0075 0.0098 d 4.80 5.00 0.1890 0.1969 e 3.80 4.00 0.1496 0.1575 e 1.27 C C 0.0500 C C h 5.80 6.20 0.2283 0.2441 h 0.25 0.50 0.0098 0.0197 l 0.40 0.90 0.0157 0.0354 a 0 8 0 8 n8 8 cp 0.10 0.0039 figure 17. so8 - 8 lead plastic small outline, 150 mils body width, package outline drawing is not to scale. so-a e n cp b e a d c l a1 a 1 h h x 45?
mk41t56, MKI41T56 16/16 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2000 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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